1. Field of the Invention
The present invent ion relates to a semiconductor device and a method of fabricating the same. More particularly, the invention relates to a bipolar transistor and a BiCMOS device including the bipolar transistor and an MOS transistor on the same semiconductor substrate.
2. Description of the Background Art
FIG. 9 is a cross-sectional view of a conventional bipolar transistor 100. An epitaxial layer 3 is formed on a semiconductor substrate 1. A floating collector 2 is formed in a boundary between the semiconductor substrate 1 and epitaxial layer 3. An intrinsic base region 18 and an emitter region 21 are formed in the upper part of the epitaxial layer 3. These elements form the bipolar transistor 100. A collector wall 6 which pierces the epitaxial layer 3 is connected to the floating collector 2.
The epitaxial layer 3 in the upper part is connected to an external base regoin 17 which is connected to the intrinsic base region 18. A base electrode 15 is connected from above to the external base region 17, and is insulated from the epitaxial layer 3 by selectively formed insulator films 5.
An emitter extracting electrode 20 is connected from above to the emitter region 21, and is insulated from the base electrode 15 by insulator films 16 and side walls 19 made of insulative material. The bipolar transistor 100 is fabricated in the manner described below. Initially, the insulator film 5 is formed over the epitaxial layer 3, and a desired resist pattern 13 is formed on the insulator film 5, as shown in FIG. 10. Anisotropic etching is performed on the insulator film 5 using the resist pattern 13 as a mask to form a desired opening in the insulator film 5 as shown in FIG. 11. This permits cross sections 14 of the insulator film 5 to appear. The regions 17, 18, 21 and electrodes 15, 20 are then formed.
This type of bipolar transistor is used in a BiCMOS device further including a MOS transistor.
The opening of the insulator film is thus formed above the base region of the conventional bipolar transistor. The cross section 14 of the insulator film 5 is approximately perpendicular to the semiconductor substrate 1. This causes the problem of deteriorating coverage of the base electrode 15 formed after the opening of the insulator, resulting in an increasing base resistance.
Another problem arises in formation of the BiCMOS device including the bipolar transistor 100 shown in FIG. 9. This type of BiCMOS device is disclosed in Japanese Patent Application Laid-Open No. 2-253654, for example. The steps described below are carried out to form a BiCMOS device 300 shown in FIG. 15 which includes the bipolar transistor 100 and an MOS transistor 200.
A layer the conductivity type of which is opposite to that of the semiconductor substrate 1 is formed in the lower part of a region in which the bipolar transistor 100 is to be formed on the semiconductor substrate 1. Epitaxial growth is performed to form the buried layer 2 and epitaxial layer 3. A well 4 is formed in the lower part of a region in which the MOS transistor 200 is to be formed. The insulator films 5 are selectively formed by means of the LOCOS process and the like. The collector wall 6, a gate insulator film 7 and a gate electrode 8 are formed in this order. Ion implantation using the gate insulator film 7 and gate electrode 8 as a mask is performed to form source-drains 9 of low concentration. After the formation of an insulator film over the top surface, anisotropic etching is performed on the insulator film to the depth equivalent to the thickness of the insulator film to form side walls 10 on the end faces of the gate electrode 8. Source-drains 11 of high concentration are formed by ion implantation. The MOS transistor 200 is completed (in FIG. 12).
In the fabrication of the MOS transistor 200, the insulator films 5 isolate the MOS transistor 200 from the region in which the bipolar transistor 100 is to be formed and protect the epitaxial layer 3 in this region from damages during the formation of the side walls 10.
The insulator film 5 is etched by using the resist pattern 13 to expose the epitaxial layer 3. After the appearance of an opening H, implantation of ions the conductivity type of which is the same as that of the semiconductor substrate 1 is performed by using the same resist pattern 13, so that the intrinsic base region 18 is formed (in FIG. 13). At this time, the insulator films 5 present the cross sections 14.
The resist pattern 13 is removed, and polycrystalline silicon is formed over the structure obtained in the foregoing steps. Implantation of ions is performed, the conductivity type of which is the same as that of the semiconductor substrate 1, and the insulator films 16 are formed. The insulator films 16 and polycrystalline silicon are etched by using a resist pattern (not shown) for the base electrode. The remaining polycrystalline silicon becomes the base electrodes 15. Impurities are diffused from the base electrodes 15 to the epitaxial layer 3 by heat treatment to form the external base region 17 (in FIG. 14).
The side walls 19 are formed on the end faces of the base electrodes 15 and insulator films 16 in the similar manner as the formation of the side walls 10. polycrystalline silicon is formed over the base regions 17, 18. Implantation of ions the conductivity type of which is opposite to that of the semiconductor substrate 1 is performed on the polycrystalline silicon, which is then etched by using a resist pattern (not shown) for the emitter electrode. The remaining polycrystalline silicon becomes the emitter electrode 20. The impurities implanted in the emitter electrode 20 are diffused to the intrinsic base region 18 by heat treatment, so that the emitter region 21 is formed (in FIG. 15).
In the fabrication of the BiCMOS device 300 as above mentioned, overetching when the base electrodes 15 are formed causes the surface of the epitaxial layer 3 to be etched so that the depth of the intrinsic base region 18 is reduced. This introduces the problems of deterioration of an emitter-collector breakdown voltage BV.sub.CEO of the bipolar transistor 100 and fluctuation in characteristics of the bipolar transistor 100 due to the amount of overetching. Overetching when the base and emitter electrodes 15 and 20 are formed causes the surface of the source-drains 11 of high concentration to be etched. This introduces the problem of an increasing sheet resistance and an increasing leak between the source-drains 9, 11 and well 4. When the gate electrode 8 is made of material which is etched during the formation of the electrodes 15 and 20, such as polycrystalline silicon, the thickness of the gate electrode 8 is similarly reduced, resulting in the increasing sheet resistance.